RTSS 2020

Accepted Brief Presentations

Brief presentations (18 out of 26 submissions)

Session A (Dec. 2)

Work-in-Progress papers (WiP)
  1. Towards representative measurement protocols.
    Kossivi KOUGBLENOU, Rihab Bennour, Adriana Gogonel and Liliana Cucu-Grosjean
  2. Fault Tolerance in a Two-State Checkpointing Regularity-Based System .
    Elena Torre and Albert Cheng
  3. Control-Flow Migration for Data-Locality Optimisation in Multi-Core Real-Time Systems.
    Stefan Reif, Phillip Raffeck, Peter Ulbrich and Wolfgang Schröder-Preikschat
  4. Designing a Server-Side Progressive JPEG Encoder for Real-Time Applications.
    Andrew Louie and Albert Cheng
  5. The ILP-Tractability of Schedulability Analysis Problems.
    Sanjoy Baruah
  6. Toward Precomputation in Real-Time Mixed-Trust Scheduling.
    Dionisio de Niz, Bjorn Andersson, Hyoseung Kim, Mark Klein and John Lehoczky
  7. Towards a fine-grain thermal model for uniform multi-core processors.
    Javier Pérez Rodríguez and Patrick Meumeu Yomsi
Conference papers never presented (CnP)
  1. Hiding DRAM Refresh Overhead in Real-Time Cyclic Executives.
    Xing Pan and Frank Mueller
Journal papers never presented (JnP)
  1. Bridging the Gap between Formal Verification and Schedulability Analysis: The Case of Robotics.
    Mohammed Foughali and Pierre-Emmanuel Hladik
  2. Schedulability Analysis of Time-Sensitive Networks with Preemption Support.
    Lucia Lo Bello, Mohammad Ashjaei, Gaetano Patti and Moris Behnam
  3. Improving WCET Evaluation using Linear Relation Analysis.
    Pascal Raymond, Claire Maiza, Catherine Parent-Vigouroux, Erwan Jahier, Nicolas Halbwachs, Fabienne Carrier, Mihail Asavoae and Rémy Boutonnet

Session B (Dec. 3)

Work-in-Progress papers (WiP)
  1. Lessons learnt from creating Extreme Value Libraries in Python.
    Marwan Wehaiba El Khazen, Adriana Gogonel and Liliana Cucu-Grosjean
  2. WCRT Analysis for the 3-Phase Task Model in Partitioned Scheduling.
    Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen and Eduardo Tovar
  3. Fine-Grained On-Chip Energy Measurement of a Real-Time Multi-Core Processor.
    Dominic Oehlert, Edward Umaña Williams and Heiko Falk
  4. Safe and Secure Configuration Synthesis for TSN using Constraint Programming.
    Niklas Reusch, Paul Pop and Silviu Craciunas
Journal papers never presented (JnP)
  1. Expression Caching for Runtime Verification Based on Parameterized Probabilistic Models.
    Hiroyuki Nakagawa, Hiromu Toyama and Tatsuhiro Tsuchiya
Work-in-Progress papers (WiP)
  1. A DSL for the safe deployment of Runtime Monitors in Cyber-Physical Systems.
    Giann Spilere Nandi, David Pereira, José Proença and Eduardo Tovar
  2. Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges.
    Gabriella D’Andrea and Giacomo Valente
Demo Presentations